Field of the Invention
The present invention relates to a connector adapter that receives an electronic component. More particularly, the present invention relates to a connector adapter package that receives a discrete electronic component and connects the discrete component to contacts intended for larger sized components.
Background of the Invention
FIG. 1 shows a traditional backplane construction having three substrates or printed circuit boards (PCB), for instance whereby two daughtercards PCBs 30, 40 are connected to each other across a backplane PCB 50. The daughtercards 30 are each electronically connected to the backplane 50 by a respective orthogonal electrical connector 201, 202, each having an electronic component 32, 42 such as a processing device (e.g., transmitter, receiver, processor, etc.). In a basic illustrative embodiment, the processing device 32 communicates with the processing device 42 by transmitting a signal along a signal path. Signals are sent by the processing device 32 across the board traces and the vias 341, 342, through the board 30 to the vias 381, 382 and to the first connector 201. The signals then travel from the first connector 201 through the backplane vias 521, 522, and then the second connector vias 541, 542 and to the second connector 202. The signals then continue to travel from the second connector 202, through the daughtercard vias 481, 482 to the processing device vias 441, 442 and to the processing device 42.
As discussed in U.S. Pat. No. 7,285,018 to Kenny which is hereby incorporated by reference, there is often the need to use a passive circuit element in the signal path. These passive circuit elements, such as capacitors, inductors, and resistors can be used to (a) block or reduce the flow of direct current caused by potential differences between electronic components 32, 42, (b) provide desired filtering characteristics, and/or (c) reduce data transmission losses. To address these issues, passive circuit elements 101, 102 have been added directly to the board 30 and/or board 40 respectively, as shown in FIG. 1A, and capacitors 102 are sometimes located as close as possible to the pins of the receiver 42 (as opposed to on the transmit side in the embodiment shown in FIG. 1A).
Surface-mount technology (SMT) is a method for producing electronic circuits in which electronic surface-mounted devices (SMDs) or surface-mounted components (SMCs) are mounted or placed directly onto the surface of printed circuit boards (PCBs). The SMDs or SMCs are made in standardized package shapes and sizes. For instance, a package size “0402” device has rectangular size with a width of 0.50 mm, a height of 0.50 mm, and a length of 1.00 mm; a “0201” device is half that size, with a width of 0.25 mm, height of 0.25 mm, and a length of 0.50 mm; and a “01005” device has a width of 0.12 mm, height of 0.12 mm, and length of 0.25 mm. The size of the device can affect the value and application of the package. For instance a “0402” capacitor can have a capacitance of 100 Picofarads, whereas a 01005 capacitor has a capacitance of 50 Picofarads.
An example of a standard discrete passive device 10 for a capacitor (which can be used for the capacitors 101, 102 of FIG. 1A) is shown in FIG. 1B. The discrete device (or package) 10 includes two end terminals or members 121, 122 and a center body member 14 extending from one end member 121 to the other end member 122. The capacitor package 10 is shown in block form and the end members 121, 122 enlarged (with respect to the body) for ease of illustration, with the package 10 having a generally rectangular elongated shape. The center body member 14 is rectangular, and the end members 121, 122 are rectangular, with a longitudinal axis of the center body member 14 extending substantially perpendicular to the longitudinal axis of the end members 121, 122. Thus, the center body 14 has two opposite ends, and an end terminal 12 is located at each of those ends. The end members 121, 122 are longer than the width of the center body member 14, as shown. The end members 121, 122 each have a top surface or face 13, side surfaces or faces 15, a bottom surface or face 16, and an end surface or face 18. Each of the package sizes, 0402, 0201 and 01005, have a similar shape, and only differ in size. It should be recognized, however, that any suitable shape and size can be provided, and for instance the package 10 need not be rectangular in shape and the end members 121, 122 need not be wider than the center body member 14.
Referring to FIG. 1A, when the passive circuit element 101, 102 are located on the board 30, 40, it takes up precious space on the board surface and contributes to SDD21 signal attenuation. In addition, the passive circuit vias 351, 352, and vias 451, 452 respectively, can create capacitance and reflection in the through holes, reflections of the via stubs, skews caused by the lack of routing space, plated through-hole defects (voids and cracks), back drilling errors/tolerances, localized cross talk between vias and traces, and uses valuable switch card space in high traffic areas.
One technique for addressing those issues is disclosed in U.S. Pat. No. 8,591,257 to Girard et al., which is incorporated herein by reference. In that patent, the passive circuit packages are placed in the connector wafer 201 and/or 202, rather than on the board 30, 40 so that the capacitors 101, 102 are not needed. As illustrated in the wafer 20 of FIGS. 2A and 2B, openings 22 are provided in the wafer housing (over mold 23) to expose a conductor 24 of the lead frame. A gap 26 is created in the conductor 24, resulting in two conductor ends 24a, 24b, and the package 10 is placed across the gap to connect with the conductor ends 24a, 24b. The bottom face 16 of the end members 121, 122 are adhered to the top surface of the exposed ends 24a, 24b of the conductor 24, such as by an adhesive or solder. As best shown in FIG. 2B, the wafer 20 includes a top layer 27 of the over mold 23, a bottom layer 28 of the over mold 23, and the conductors 24a, 24b of the lead frame positioned there between. The opening 22 is provided in the top layer 27 and the bottom layer 28 that exposes the conductor leads 24a, 24b. The package 10 is positioned inside the opening 22 in the top layer 27 to connect with the two conductors 24a, 24b of the lead frame. Packages are also shown in the connector of U.S. Pat. No. 8,382,524 to Khilchenko, which is hereby incorporated by reference.
The conductor 24 has a thickness T and the gap 26 has a width W. The width W of the gap 26 can be larger than or equal to the thickness T of the conductor 24. However, the size of the gap 26 is dependent on the thickness T of the conductor 24, because the gap 26 cannot be reliably made smaller than the thickness T of the conductor 24. Thus, the width W of the gap 26 is only made larger or equal to the thickness T of the conductor 24. And the thickness T of the conductor 24 can only be reduced to a certain extent, based on a number of factors such as: characteristic impedance Zo targets, progressive stamping die tool capabilities, normal force targets for beam design/beam strength due to normal force or spring force (e.g., minimum end of life normal force of 40 grams) for the separable mating interfaces, coined features needs and strength requirements such as those tied to press fit eye of the needle dynamic sections, resistance to damage, shape change, location changes during manufacturing processes, such as but not limited to molding, stamping, reeling, plating, assembly and handling.
Accordingly, the gap 26 has to be equal to or larger than the thickness T of the conductor 24, which means that the package 10 has to be large enough to span the gap 26. Consequently, the package (such as a capacitor) 10 of FIGS. 1-2 may be unable to electrically connect to the leads 24a, 24b of the lead frame if the package is too small to span the width W of the gap 26. More specifically, the gap 26 may be too large for the smaller package such as the 0201-sized package 5 to span the gap 24 and connect with the conductors 24a, 24b, such that only the larger package such as the 0402-sized package 10 (FIG. 1B) can be utilized. Thus, there is a need for a wafer 20 configured to electrically connect packages (such as capacitors) smaller than the package 10 of FIG. 1B between the leads 24a, 24b of the lead frame.
Another technique to address the issues faced by having a passive circuit device package 10 on the boards 30, 40 is shown in U.S. Pat. No. 8,241,067 to Girard, Jr. et al., which is hereby incorporated by reference. In that patent, the capacitor is located on the board close to one of the signal conductor tails of the connector. The capacitor does not have its own vias (as in FIG. 1 above), but instead shares a via with that signal conductor tail.